1. Field of the Invention
The present invention relates to a digital/analog converter, and more particularly, to a digital/analog converter capable of controlling adjacent switching elements, of which the number is a multiple of a predetermined number, using one decoder to reduce an RC delay caused by the adjacent voltage dividing elements, thereby improving an operation speed.
2. Description of the Related Art
Digital/analog converters are devices that convert digital signals into analog signals. The digital/analog converter is generally used to convert digital data values into analog signals when a user inputs a digital control code during an image sensing process and sets up the range of digital data values that are stored according to the brightness of images.
In general, a method of using a row of resistors, a method of using capacitors, and a method of using current cells are used to divide a voltage in the digital/analog converter.
However, the known methods have a problem in that an RC delay occurs between adjacent voltage dividing elements, which results in a low operation speed.
Next, the problems of the digital/analog converter according to the related art will be described in detail with reference to the accompanying drawings.
FIG. 1 is a circuit diagram illustrating a digital/analog converter according to the related art, FIG. 2 is a diagram illustrating an RC delay of the digital/analog converter according to the related art, and FIG. 3 is a diagram illustrating a grayscale error of the digital/analog converter according to the related art.
First, as shown in FIG. 1, the digital/analog converter according to the related art includes: a voltage dividing unit 10 that includes a plurality of voltage dividing elements; a first decoder 30 that selects a plurality of voltages among the voltages divided by the voltage dividing unit 10; a first voltage output unit 20 that is connected to the voltage dividing unit 10 and the first decoder 30 and is controlled by the first decoder 30 to output a plurality of voltages divided by the voltage dividing unit 10; a second decoder 40 that selects a predetermined voltage from the plurality of voltages output from the first voltage output unit 20; and a second voltage output unit 50 that is connected to the first voltage output unit 20 and the second decoder 40 and is controlled by the second decoder 40 to output a predetermined voltage among the plurality of voltages output from the first voltage output unit 20.
The voltage dividing unit 10 includes 256 voltage dividing elements R1 to R256 connected in series to one another, and has one end supplied with a reference voltage VDD and the other end connected to the ground GND of the circuit. In addition, predetermined divided voltages are output from nodes among the voltage dividing elements R1 to R256. In this case, resistors, capacitors, or current cells may be used as the plurality of voltage dividing elements R1 to R256.
The first voltage output unit 20 includes a plurality of voltage selecting units 20a to 20p, and the voltage selecting units 20a to 20p each include 16 switching elements S1 to S16, . . . S241 to S256 that are connected to the corresponding nodes in each group of 16 voltage dividing elements among the voltage dividing elements R1 to R256 of the voltage dividing unit 10.
For example, the first voltage selecting unit 20a includes the first to sixteenth switching elements S1 to S16 that are connected to the corresponding nodes among the first to sixteenth voltage dividing elements R1 to R16, and the second voltage selecting unit 20b includes the seventeenth to thirty-second switching elements S17 to S32 that are connected to the corresponding nodes among the seventeenth to thirty-second voltage dividing elements R17 to R32. In particular, the switching elements S1 to S256 of each of the first to sixteenth voltage selecting units 20a to 20p are connected to the same output terminal of the first decoder 30 such that they are simultaneously controlled by the first decoder 30.
Further, the first decoder 30 receives a digital signal of 8 bits a0 to a7 from the outside and is controlled by four most significant bits a0 to a3 of the digital signal to select any one of the 16 voltage selecting units 20a to 20p. 
That is, the first decoder 30 outputs a high-level selection signal to any one of the 16 output terminals C1 to C16 by the four most significant bits a0 to a3 of the digital signal of 8 bits a0 to a7 received from the outside, and one of the 16 voltage selecting units 20a to 20p having received the high-level selection signal outputs a divided voltage from the voltage dividing unit 10 connected thereto.
Furthermore, the second decoder 40 outputs a high-level selection signal to any one of the 16 output terminals C1 to C16 by four least significant bits a4 to a7 of the digital signal of 8 bits a0 to a7 received from the outside to select any one of the 16 voltages output from the first voltage output unit 20.
The second voltage output unit 50 includes a plurality of switching elements S1a to S16a, and each of the plurality of switching elements S1a to S16a has a gate connected to a corresponding one of the output terminals C1 to C16 of the second decoder 40 and one end connected to the first voltage output unit 20. Therefore, the switching elements S1a to S16a are turned on or off by selection signals output from the second decoder 40. When any one of the switching elements S1a to S16a is turned on by the second decoder 40, a voltage Vout is output from the second voltage output unit 50.
If the first decoder 30 outputs the high-level selection signal to the first output terminal C1 by four most significant bits of the digital signal of 8 bits a0 to a7 received from the outside, all the switching elements S1 to S16 of the first voltage selecting unit 20a having received the high-level selection signal are turned on, and the voltages divided by the first to sixteenth voltage dividing elements R1 to R16 are output.
If the second decoder 40 outputs the high-level selection signal to the second output terminal C2 by four least significant bits of the digital signal of 8 bits a0 to a7, the switching element S2a of the second voltage output unit 50 having received the high-level selection signal is turned on, and the voltage divided by the second voltage dividing element R2 among the voltages output from the first voltage selecting unit 20a is output as a final output voltage Vout.
However, in the digital/analog converter having the above-mentioned structure according to the related art, since the voltages divided by 16 adjacent voltage dividing elements among the voltage dividing elements R1 to R256 are selected by the first decoder 30 and then output by the first voltage output unit 20 at the same time, the voltages are affected by the adjacent voltage dividing elements, resulting in an RC delay.
In this case, as shown in FIG. 2, when the user wants a data waveform A, a waveform A′ is not output, but a waveform B having a time delay to reach a peak value due to the RC delay is output, which results in delay in operation.
As a result, as shown in FIG. 3, even though a voltage corresponding to Vout1 is output at a time t1, a voltage Vout2 lower than the voltage Vout1 is output at the time t1 due to the RC delay caused by 16 adjacent voltage dividing elements R1 to R16, . . . , R241 to R256, which makes it difficult to accurately represent desired brightness and color, resulting in a grayscale error.